Dynamic random access memory cells have been widely used in modern semiconductor devices. The cells have been named as dynamic because they can retain information only for a limited time and must be read and refreshed periodically. This is in contrast to a static random access memory cell which does not require periodic refresh signals in order to retain stored data. In a typical DRAM cell, the structure includes a transistor and a storage node (or storage capacitor). When DRAM cells were first developed, planar type storage capacitors which occupy large wafer surface areas are used. As the circuit density increases in modern semiconductor devices where smaller chips are being made and are being packed with ever-increasing number of circuits, the specific capacitance of a storage capacitor must be increased in order to meet such demands.
Different approaches have been used in achieving higher capacitance in the storage node while limiting usage of wafer real estate. For instance, one solution is to store charges vertically in a trench which requires a deep trench formation and encounters significant processing difficulties. The second solution is to build a stacked capacitor on top of the transistor which allows a smaller cell to be built without losing storage capacity. The solution of using a stacked capacitor has become a more accepted and popular approach in the semiconductor fabrication industries.
In modem DRAM cells, small dimension and high capacitance value per unit area are therefore desirable characteristics for achieving high charge storage capacity. A DRAM storage node is normally formed by at least two layers of semi-conducting material and one layer of a dielectric material. For example, a widely used DRAM storage node utilizes a thin oxide layer sandwiched between two polysilicon layers to produce a high capacitance node cell. The node can be built by stacking over the bit line on the surface of a silicon substrate. The effective capacitance of a stacked cell is increased over that of a conventional planar cell due to its increased surface area.
A typical 16-Mb DRAM cell 10 having a stacked storage node 20 built on top is shown in FIG. 1. The DRAM cell 10 can be formed in the following manner. First, standard CMOS fabrication steps can be used to form the transistors and the gate oxide layer. To form the word lines 12, a first polysilicon layer of approximately 2,500 .ANG. thick is deposited and then doped with phosphorous. A thick layer of insulating material 16 such as TEOS (tetraethoxy silicate) oxide of approximately 3,000 .ANG. is then deposited on top of the first polysilicon layer. By using standard photomasking processes, the two layers are etched by a plasma etching technique as a stack. After LDD implants are made in the silicon substrate, oxide spacers are formed on the polysilicon gate structure by depositing a thick layer of TEOS oxide of approximately 2,000 .ANG. and then etched in a plasma process. Gates 12 and 14 are thus formed and covered by a thick insulating layer 16 of oxide. A source and drain mask is then applied for an ion implantation process to form the source and drain regions in the silicon substrate.
In the next fabrication step, photomasking is used to form window openings for the cell contact and plasma etching is used to remove any native oxide layer on the silicon substrate. A second polysilicon layer 22 of approximately 3,500 .ANG. is deposited and patterned by a photomask to form the lower electrode of the storage node 20. A dielectric layer 24 of a composite film of oxidenitride-oxide (ONO) is then deposited as the dielectric layer for the storage node. The total thickness of the ONO composite film is approximately 70 .ANG.. The ONO composite film can be formed by using a thin layer of native oxide as the first oxide layer, depositing a thin nitride layer on top and then oxidizing the nitride layer to grow a top oxide layer. To complete the fabrication of the storage node, a third polysilicon layer 24 of approximately 2,000 .ANG. thick is deposited on top of the dielectric layer and then doped and patterned by a photomask to form an upper electrode. After the formation of the stacked capacitor, peripheral devices can be formed by masking and ion implantation, followed by the formation of a bit line 28 of a polysilicon/metal silicide material. A thick insulating layer 32 of BPSG or SOG is then deposited over the capacitor and reflowed to smooth out the topography and to reduce the step height. Other back-end-processes such as metalization to form metal lines 34 are used to complete the fabrication of the memory device 10.
The stacked capacitor 10 shown in FIG. 1 has been successfully used in 16 Mb DRAM devices. However, as device density increases in ULSI devices and beyond, the planar surface required for building the conventional stacked capacitors becomes excessive and can not be tolerated. Furthermore, the topography of the device formed in FIG. 1 requires a difficult planarization process to be performed on the DRAM device. For instance, a low cost and reliable method of chemical mechanical polishing (CMP) can not be used.
It is therefore an object of the present invention to provide a method for forming DRAM storage node that does not have the drawbacks or shortcomings of the prior art methods for forming storage node.
It is another object of the present invention to provide a method for forming DRAM storage node which only requires a deposit of a single layer of insulating material on a pre-processed semi-conducting substrate for forming the node.
It is a further object of the present invention to provide a method for forming DRAM storage node that can be readily adapted in ultra-high density semiconductor devices.
It is another further object of the present invention to provide a method for forming DRAM storage node by dry etching a node contact opening and a node tub opening sequentially in an insulating layer deposited on the surface of a pre-processed semi-conducting wafer.
It is yet another object of the present invention to provide a method for forming DRAM storage node by the sequential forming of a small node contact opening and a large node tub opening for the deposition of a polysilicon material as the lower electrode of the node.
It is still another object of the present invention to provide a method for forming DRAM storage node by the sequential formation of a large node tub opening and a small node contact opening in an insulating layer for depositing a polysilicon node material in forming the lower electrode.
It is still another further object of the present invention to provide a DRAM storage node that is formed by a crown-shaped upper portion and a column-shaped lower portion by a polysilicon material in a medium of an insulating material encasing the storage node.